Thank you for sending your enquiry! One of our team members will contact you shortly.
Thank you for sending your booking! One of our team members will contact you shortly.
Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- Understanding the open ISA philosophy and the standardization landscape established by RISC-V International
- Core mental models of RISC-V: Load-Store architecture principles, register file structures, and byte ordering conventions
- Comparative analysis with ARM, x86, and POWER architectures to evaluate trade-offs for heterogeneous computing environments
- Evaluation of ecosystem maturity, focusing on key contributors like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Overview of standardized interfaces: The RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Insights into the Unprivileged Architecture specification, including the Control and Status Register (CSR) map, exception handling mechanisms, and memory hierarchies
- Examination of RV32I and RV64I instruction sets and Application Binary Interface (ABI) compliance to ensure cross-platform binary portability
- Strategies for managing memory ordering conventions and utilizing barrier instructions in multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Mastery of base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Programming techniques adapted for bitness, covering both 32-bit and 64-bit RISC-V targets
- Implementation of calling conventions and stack frame management tailored for embedded and real-time software systems
Compiler Toolchain Proficiency
- Utilization of the LLVM-based compiler toolchain, including Clang, LLVM, and Binutils for cross-compiling RISC-V code
- Configuration of linker scripts, sections, and memory layouts for bare-metal and Real-Time Operating System (RTOS) environments
- Application of compiler intrinsics, selection of optimization levels, and profiling-driven code tuning strategies
- Workflows for developing open-source toolchains, including building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Systems programming in Rust for RISC-V, focusing on zero-cost abstractions, unsafe memory management, and bare-metal development practices
- Development in No-Std environments, including custom linkers, device driver creation, and memory-mapped I/O handling
- Implementation of Zephyr RTOS and Buildroot Board Support Package (BSP) development for RISC-V targets
- Peripheral interfacing techniques covering GPIO, I2C, SPI, UART, and DMA controller programming
Power and Performance Optimization
- Techniques for clock gating, power domain management, and optimizing low-power modes
- Cycle-accurate performance analysis using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency to meet the requirements of safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Development of bootloader firmware using OpenSBI, which implements the SBI specification
- Implementation of modern firmware boot stacks via UEFI/EDK II on RISC-V platforms
- Porting Coreboot and U-Boot to support RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel, including device tree overlays, CPU topology management, and interrupt controller (AIA) driver development
- Development of Vendor BSPs and kernel configuration for custom SoC platforms
- Support for file systems, networking stacks, and containerization technologies (such as Docker and Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Application of Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Implementation of Axi4/CHI cache coherence and inter-processor communication protocols
- Integration of open-source IP cores from OpenCores and the ChIPS Framework, alongside vendor-provided RTL components
- Design of bus matrices and integration of memory controllers supporting DDR, SRAM, eMMC, and PCIe interfaces
FPGA-Based Processor Prototyping
- Synthesis and implementation of RISC-V cores on FPGA platforms (e.g., BOOM, VexRiscv, PULP)
- Application of SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Use of formal verification tools and property-based testing for rigorous RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Mechanisms for vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration
- Leveraging variable-length vector operations (VL, VLEN) to optimize SIMD execution for specific workloads
- Utilization of vector mask operations, segment control, and data type flexibility to support DSP and machine learning (ML) tasks
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators through custom ISA extensions and CBAR-based operand interfaces
- Modifying compiler frontends to facilitate custom instruction generation and code emission
- Strategies for hardware-software partitioning to effectively integrate accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units (NPUs) using systolic arrays, tensor cores, and weight compression techniques for on-chip AI acceleration
- Applying model quantization methods (INT8, INT4, FP8) suitable for edge deployment on RISC-V hardware
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing the interaction between RISC-V host CPUs and AI accelerator NPUs for real-time inference pipelines
- Optimizing the memory subsystem, particularly managing HBM/DDR bandwidth for ML model weights and activations
- Managing thermal constraints and power budgets in edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementation of Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Development of Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments
- Establishing boot chain security through root of trust, secure boot processes, and measured launch attestation
Cryptographic Acceleration
- Utilization of RISC-V cryptographic extensions (Zk, Zkr, K extensions) for accelerating SHA, AES, RSA, RSA-PSS, and ECC operations
- Integration of Post-Quantum Cryptography (PQC) techniques for next-generation RISC-V processors
- Implementation of side-channel attack mitigation strategies, including constant-time programming, masking, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Methodology for designing ISA extensions: encoding schemes, encoding tables, ABI impact analysis, and the submission process to RISC-V International
- Designing custom register files utilizing CBAR (Custom Base Address Registers) for efficient operand dispatch
- Optimizing instruction pipelining, hazard detection, and making pipeline modifications necessary for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions, distinguishing between directed stimulus generation and constraint-random testing
- Implementing regression testing frameworks and coverage-driven verification processes for architectural modifications
- Conducting interoperability testing to ensure custom instructions operate correctly within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors
- Defining ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection schemes for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and implementing deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways with RISC-V, focusing on connectivity, edge analytics, and Over-The-Air (OTA) firmware update capabilities
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: Designing ISA extensions and core configurations for a specific use case
- RTL implementation in SystemVerilog, supported by UVM testbenches and formal verification coverage analysis
- FPGA prototyping, boot firmware development, and integration of the bare-metal driver stack
- Customization of the Linux BSP and toolchain for the newly designed RISC-V core
- Deployment of AI workloads, including NPU integration, model quantization, and performance benchmarking
- Security validation: Enforcing PMP policies, implementing secure boot, and benchmarking cryptographic acceleration
- Production of technical architecture documentation, IP strategy analysis, and presentation to cross-functional teams
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
